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LXT351
T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation
Datasheet
The LXT351 is a full-featured, fully-integrated transceiver for T1 and E1 short-haul applications. The LXT351 is software switchable between T1 and E1 operation, and offers pulse equalization settings for all short-haul T1 and E1 line interface (LIU) applications. The LXT351 offers an Intel/Motorola compatible parallel port for microprocessor control. The device incorporates advanced crystal-less digital jitter attenuation in either the transmit or receive data path starting at 3 Hz. B8ZS/HDB3 encoding/decoding and unipolar or bipolar data I/O are selectable. Loss of signal monitoring and a variety of diagnostic loopback modes can also be selected.
Applications
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SONET/SDH tributary interfaces Digital cross connects
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Public/private switching trunk line interfaces Microwave transmission systems
Product Features
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Fully integrated transceivers for Short-Haul T1 or E1 interfaces Crystal-less digital jitter attenuation -- Select either transmit or receive path -- No crystal or high speed external clock required Meet or exceed specifications in ANSI T1.403 and T1.408; ITU I.431, G.703, G.736, G.775 and G.823; ETSI 300-166 and 300-233; and AT&T Pub 62411 Supports 75 (E1 coax), 100 (T1 twisted-pair) and 120 (E1 twisted-pair) applications Fully restores the received signal after transmission through a cable with attenuation of 18dB, at 1024 kHz Five pulse equalization settings for T1 short-haul applications
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Transmit/receive performance monitors with Driver Fail Monitor Open (DFM) and Loss of Signal (LOS) outputs Selectable unipolar or bipolar data I/O and B8ZS/HDB3 encoding/decoding QRSS generator/detector for testing or monitoring Output short circuit current limit protection Local, remote and analog loopback capability Compatible with Intel's LXT360/361 T1/ E1 long haul/short haul transceiver (Universal LIU) Multiple register parallel interface compatible with both Intel and Motorola microprocessors Available in 28-pin PLCC and 44-pin PQFP packages
As of January 15, 2001, this document replaces the Level One document Order Number: 249030-001 LXT351 -- Integrated T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation. January 2001
Information in this document is provided in connection with Intel(R) products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The LXT351 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800548-4725 or by visiting Intel's website at http://www.intel.com. Copyright (c) Intel Corporation, 2001 *Third-party brands and names are the property of their respective owners.
Datasheet
T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation -- LXT351
Contents
1.0 2.0 Pin Assignments and Signal Descriptions......................................................8
1.1 2.1 2.2 Mode Dependent Signals ...................................................................................... 9 Initialization..........................................................................................................13 2.1.1 Reset Operation .....................................................................................13 Transmitter ..........................................................................................................13 2.2.1 Transmit Digital Data Interface...............................................................13 2.2.2 Transmit Monitoring................................................................................14 2.2.3 Transmit Drivers .....................................................................................14 2.2.4 Transmit Idle Mode.................................................................................14 2.2.5 Transmit Pulse Shape ............................................................................14 Receiver ..............................................................................................................15 2.3.1 Receive Data Recovery..........................................................................15 Jitter Attenuation .................................................................................................15 Diagnostic Mode Operation.................................................................................16 2.5.1 Loopback Modes ....................................................................................16 2.5.1.1 Local Loopback .........................................................................16 2.5.1.2 Analog Loopback.......................................................................18 2.5.1.3 Remote Loopback .....................................................................18 2.5.1.4 Dual Loopback ..........................................................................19 2.5.2 Internal Pattern Generation ....................................................................19 2.5.2.1 Transmit All Ones ......................................................................19 2.5.2.2 Quasi-Random Signal Source (QRSS) .....................................20 2.5.3 Error Insertion and Detection .................................................................21 2.5.3.1 Bipolar Violation Insertion (INSBPV) .........................................21 2.5.3.2 Logic Error Insertion (INSLER)..................................................21 2.5.3.3 Bipolar Violation Detection (BPV)..............................................21 2.5.3.4 HDB3 Code Violation Detection (CODEV) ................................21 2.5.3.5 HDB3 Zero Substitution Violation Detection (ZEROV) ..............21 2.5.4 Alarm Condition Monitoring ....................................................................22 2.5.4.1 Loss of Signal ............................................................................22 2.5.4.2 Alarm Indication Signal Detection .............................................22 2.5.4.3 Driver Failure Open Mode .........................................................22 2.5.4.4 Elastic Store Overflow/Underflow ..............................................22 2.5.4.5 Built-In Self Test ........................................................................23 Parallel Microprocessor Interface........................................................................23 2.6.1 Interrupt Handling...................................................................................23
Functional Description...........................................................................................13
2.3 2.4 2.5
2.6
3.0 4.0
Register Definitions.................................................................................................24 Application Information.........................................................................................29
4.1 4.2 4.3 4.4 Transmit Return Loss ..........................................................................................29 Transformer Data ................................................................................................29 Application Circuit................................................................................................29 Line Protection ....................................................................................................29 4.4.1 LXT351 Application Circuit .....................................................................31
Datasheet
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LXT351 -- T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation
5.0 6.0
Test Specifications.................................................................................................. 33 Mechanical Specifications ................................................................................... 45
Figures
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 LXT351 Block Diagram ......................................................................................... 7 LXT351 Pin Assignments...................................................................................... 8 50% Duty Cycle Coding ...................................................................................... 14 Local Loopback ................................................................................................... 16 TAOS with LLOOP .............................................................................................. 17 Analog Loopback ................................................................................................ 18 Remote Loopback ............................................................................................... 19 Dual Loopback .................................................................................................... 19 TAOS Data Path ................................................................................................. 20 QRSS Mode ........................................................................................................ 20 Typical T1/E1 LXT351 Application ...................................................................... 32 2.048 Mbps E1 Pulse (See Table 24)................................................................. 35 1.544 Mbps T1 Pulse, DSX-1 (See Table 25) ..................................................... 36 Transmit Clock Timing ........................................................................................ 37 Receive Clock Timing ......................................................................................... 38 Intel Address/Data Bus Timing............................................................................ 40 Motorola Address/Data Bus Timing .................................................................... 41 Typical T1 Jitter Tolerance at 36 dB ................................................................... 41 Typical E1 Jitter Tolerance at 43 dB ................................................................... 42 Typical E1 Jitter Attenuation ............................................................................... 43 Typical T1 Jitter Attenuation................................................................................ 44 Plastic Leaded Chip Carrier Package Specifications .......................................... 45 Plastic Quad Flat Package Specifications........................................................... 46
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Datasheet
T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation -- LXT351
Tables
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 LXT351 Clock and Data Pin Assignments by Mode1............................................ 9 LXT351 Processor Interface Pins.......................................................................... 9 LXT351 Signal Descriptions ................................................................................10 Diagnostic Mode Summary .................................................................................16 Register Addresses .............................................................................................24 Register and Bit Summary ..................................................................................24 Control Register #1 Read/Write, Address (A7-A0) = x010000x ..........................25 Equalizer Control Input Settings.........................................................................25 Control Register #2 Read/Write, Address (A7-A0) = x010001x ..........................25 Control Register #3 Read/Write, Address (A7-A0) = x010010x ..........................26 Interrupt Clear Register Read/Write, Address (A7-A0) = x010011x....................26 Transition Status Register Read Only, Address (A7-A0) = x010100x.................27 Performance Status Register Read Only, Address (A7-A0) = x010101x ............27 Control Register #4 Read/Write, Address (A7-A0) = x010111x ..........................28 E1 Transmit Return Loss Requirements .............................................................29 Transmit Return Loss (2.048 Mbps)....................................................................30 Transmit Return Loss (1.544 Mbps)....................................................................30 Transformer Specifications..................................................................................30 Recommended Transformers..............................................................................31 Absolute Maximum Ratings.................................................................................33 Recommended Operating Conditions .................................................................33 DC Electrical Characteristics...............................................................................34 Analog Characteristics ........................................................................................34 2.048 Mbps E1 Pulse Mask Specifications ........................................................35 1.544 Mbps T1, DSX-1 Pulse Mask Corner Point Specifications........................36 Master and Transmit Clock Timing Characteristics for T1 Operation (See Figure 14) ...................................................................................................37 Master and Transmit Clock Timing Characteristics for E1 Operation (See Figure 14) ...................................................................................................37 Receive Timing Characteristics for T1 Operation (See Figure 15)......................38 Receive Timing Characteristics for E1 Operation (See Figure 15) .....................38 20 MHz Intel Bus Parallel I/O Timing Characteristics (See Figure 16)................39 16.78 MHz Motorola Bus Parallel I/O Timing Characteristics (See Figure 17) ...40
Datasheet
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LXT351 -- T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation
Revision History
Revision Date Description
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Datasheet
T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation -- LXT351
Figure 1. LXT351 Block Diagram
Datasheet
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LXT351 -- T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation
1.0
Pin Assignments and Signal Descriptions
Figure 2. LXT351 Pin Assignments
TPOS / TDATA / INSLER
TNEG / INSBPV
MCLK
TCLK
AD5
AD4 27
4 ALE / AS RNEG / BPV RPOS / RDATA RCLK RD / DS AD6 AD7 5 6 7 8 9 10 11 12 WR / R/W
3
2
1
28
26 25 24 23 AD2 AD1 AD0 GND VCC RRING RTIP
LXT351PE XX LXT351PE XXXXXX XXXXXXXX
13 TTIP 14 TGND 15 TVCC 16 TRING 17 CS 18 INT
AD3 22 21 20 19
TPOS / TDATA / INSLER
TNEG / INSBPV
MCLK
TCLK
AD5
AD4
AD3
AD2
n/c
44 43 42 41 40 39 38 37 36 35 34 n/c ALE / AS RNEG / BPV RPOS / RDATA RCLK n/c RD / DS n/c AD6 AD7 n/c 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 TGND TVCC CS n/c n/c n/c TRING TTIP WR / R/W INT n/c 33 32 31 30 n/c AD1 AD0 n/c GND n/c VCC n/c RRING RTIP n/c
n/c
n/c 29 28 27 26 25 24 23
LXT351QE LXT351QE XX XXXXXX XXXXXXXX
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Datasheet
T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation -- LXT351
1.1
Mode Dependent Signals
As shown in Figure 2, the LXT351 has several pins that change function (and signal name) according to the selected mode(s) of operation. These pins, associated signal names, and operating modes are summarized in Table 1 and Table 2. LXT351 signals are described in Table 3.
Table 1.
Pin # PLCC 1 2 3 4 6 7 8 13 16 19 20
LXT351 Clock and Data Pin Assignments by Mode1
External Data Modes QRSS Modes Bipolar Mode MCLK TCLK TPOS TNEG RNEG RPOS TDATA INSBPV BPV RDATA RCLK TTIP TRING RTIP RRING RNEG RPOS INSLER INSBPV BPV RDATA Unipolar Mode
QFP 39 41 42 43 3 4 5 15 19 24 25
Bipolar Mode
Unipolar Mode
1. Data pins change based on whether external data or internal QRSS mode is active.
Table 2.
Pin # PLCC 5 9 12 17 18 23 24 QFP 2 7 13 20 21 31 32
LXT351 Processor Interface Pins
Address/Data Bus Type Intel ALE RD WR CS INT AD0 AD1 Motorola AS DS R/W Pin # PLCC 25 26 27 28 10 11 QFP 35 36 37 38 9 10 Address/Data Bus Type Intel AD2 AD3 AD4 AD5 AD6 AD7 Motorola
Datasheet
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LXT351 -- T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation
Table 3.
Pin #
LXT351 Signal Descriptions
Symbol I/O1 Description Master Clock. External, independent clock signal required to generate internal clocks. For T1 applications, a 1.544 MHz clock is required; for E1, a 2.048 MHz clock. MCLK must be jitter-free and have an accuracy better than 50 ppm with a typical duty cycle of 50%. Upon Loss of Signal (LOS), RCLK is derived from MCLK. Transmit Clock. For T1 applications, a 1.544 MHz clock is required; for E1, a 2.048 MHz clock. The transceiver samples TPOS and TNEG on the falling edge of TCLK (or MCLK, if TCLK is not present). BIPOLAR MODES: Transmit - Positive and Negative. TPOS and TNEG are the positive and negative sides of a bipolar input pair. Data to be transmitted onto the twisted-pair line is input at these pins. TPOS/TNEG are sampled on the falling edge of TCLK (or MCLK, if TCLK is not present). UNIPOLAR MODES: Transmit Data. TDATA carries unipolar data to be transmitted onto the twisted-pair line and is sampled on the falling edge of TCLK. Transmit Insert Logic Error. In QRSS mode, a Low-to-High transition on INSLER inserts a logic error into the transmitted QRSS data pattern. The error follows the data flow of the active loopback mode. The LXT351 samples this pin on the falling edge of TCLK (or MCLK, if TCLK is not present). Transmit Insert Bipolar Violation. INSBPV is sampled on the falling edge of TCLK (or MCLK, if TCLK is not present) to control Bipolar Violation (BPV) insertions in the transmit data stream. A Low-to-High transition is required to insert each BPV. In QRSS mode, the BPV is inserted into the transmitted QRSS pattern. Address Latch Enable. Connect to ALE signal of Intel microprocessor Address Strobe Connect to AS signal of Motorola microprocessor. Note that leaving this pin floating forces all output pins to a high impedance state. BIPOLAR MODES: Receive - Negative and Positive. RPOS and RNEG are the positive and negative sides of a bipolar output pair. Data recovered from the line interface is output on these pins. A signal on RNEG corresponds to receipt of a negative pulse on RTIP/RRING. A signal on RPOS corresponds to receipt of a positive pulse on RTIP/RRING. RNEG/RPOS are Non-Returnto-Zero (NRZ). The PLCKE bit in register CR3 selects the RCLK clock edge when RPOS /RNEG are stable and valid. UNIPOLAR MODES: Receive Bipolar Violation. BPV goes High to indicate detection of a bipolar violation from the line. This is an NRZ output, valid on the rising edge of RCLK. Receive Data. RDATA is the unipolar NRZ output of data recovered from the line interface. The PLCKE bit in register CR3 selects the RCLK clock edge when RDATA is stable and valid. Receive Recovered Clock. The clock recovered from the line input signal is output on this pin. Under LOS conditions, there is a smooth transition from the RCLK signal (derived from the recovered data) to the MCLK signal at the RCLK pin.
PLCC
QFP
1
39
MCLK
DI
2
41
TCLK
DI
3 4
42 43
TPOS / TDATA / INSLER TNEG / INSBPV
DI DI
5
2
ALE / AS
DI
6 7
3 4
RNEG / BPV RPOS / RDATA
DO DO
8
5
RCLK
DO
1. DI = Digital Input; DO = Digital Output; DI/O = Digital Input/Output; AI = Analog Input; AO = Analog Output.
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Datasheet
T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation -- LXT351
Table 3.
Pin #
LXT351 Signal Descriptions (Continued)
Symbol I/O1 Description Read. On an Intel bus, driving RD Low commands a LXT351 register read operation. Data Strobe. On a Motorola bus, DS goes Low when data is being driven on the address/data bus. Data is valid on the rising edge of DS. Address/Data Bus 6 and 7. Used with AD0 - AD5 to form the address/ data bus. Conforms to Intel and Motorola multiplexed address/data bus specifications. Write. On an Intel bus, driving WR Low commands a LXT351 register write operation. Read/Write. On a Motorola bus, driving R/W High commands a LXT351 register read operation; driving it Low commands a write operation. Transmit Tip and Ring. Differential driver output pair designed to drive a 50 - 200 load. The transformer and line matching resistors should be selected to give the desired pulse height and return loss performance. See "Application Information" on page 29. Ground return for the transmit driver power supply TVCC. +5 VDC Power Supply for the transmit drivers. TVCC must not vary from VCC by more than 0.3 V. Chip Select. During a read or write operation, CS must remain Low. See Figure 16 and Figure 17 for timing requirements. In the case of a single processor controlling several chips, this line is used to select a specific transceiver. Interrupt. INT goes Low to flag the host when LOS, AIS, QRSS, DFMS or DFMO bits changes state, or when an elastic store overflow or underflow occurs. To identify the specific interrupt, read the Performance Status Register (PSR). To clear or mask an interrupt, write a one to the appropriate bit in the Interrupt Clear Register (ICR). To re-enable the interrupt, write a zero. INT is an open drain output that must be connected to VCC through a pull-up resistor. Receive Tip and Ring. The Alternate Mark Inversion (AMI) signal received from the line is applied at these pins. A 1:1 transformer is required. Data and clock recovered from RTIP/RRING are output on the RPOS/RNEG (or RDATA in Unipolar mode), and RCLK pins. +5 VDC Power Supply for all circuits except the transmit drivers. Transmit drivers are supplied by TVCC.
PLCC
QFP
9
7
RD / DS
DI
10 11
9 10
AD6 AD7
DI/O
12
13
WR / R/W
DI
13 16 14 15
15 19 16 18
TTIP TRING TGND TVCC
AO
-
17
20
CS
DI
18
21
INT
DO
19 20 21
24 25 27
RTIP RRING VCC
AI
-
1. DI = Digital Input; DO = Digital Output; DI/O = Digital Input/Output; AI = Analog Input; AO = Analog Output.
Datasheet
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LXT351 -- T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation
Table 3.
Pin #
LXT351 Signal Descriptions (Continued)
Symbol I/O1 Ground return for VCC. Description
PLCC 22 23 24 25 26 27 28
QFP 29 31 32 35 36 37 38 8, 11, 12, 14, 17, 22, 23, 26, 28, 30, 33, 34, 40, 44 GND AD0 AD1 AD2 AD3 AD4 AD5 DI/O Address/Data Bus 0 - 5. Used with AD6 and AD7 to form the address/ data bus. Conforms to Intel and Motorola multiplexed address/data bus specifications.
-
n/c
-
Not Connected
1. DI = Digital Input; DO = Digital Output; DI/O = Digital Input/Output; AI = Analog Input; AO = Analog Output.
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Datasheet
T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation -- LXT351
2.0
Functional Description
The LXT351 is a fully integrated, PCM transceiver for short-haul, 1.544 Mbps (T1) or 2.048 Mbps (E1) applications allowing full-duplex transmission of digital data over existing twisted-pair installations. It interfaces with two twisted-pair lines (one pair each for transmit and receive) through standard pulse transformers and appropriate resistors. The figure on the front page of this data sheet shows a block diagram of the LXT351. Control of the chip is via the 8-bit parallel microprocessor port. Stand-alone operation is not supported. The LXT351 provides a high-precision, crystal-less jitter attenuator (JA). The user may place the JA in the transmit or receive path, or bypass it completely. The transceiver meets or exceeds FCC, ANSI, and AT&T specifications for CSU and DSX-1 applications, as well as ITU and ETSI requirements for E1 ISDN PRI applications.
2.1
Initialization
During power up, the transceiver remains static until the power supply reaches approximately 3 V. Upon crossing this threshold, the device begins a 32 ms reset cycle to calibrate the Phase Lock Loops (PLL). The transceiver uses a reference clock to calibrate the PLLs: the transmitter reference is TCLK, and the receiver reference clock is MCLK. MCLK is mandatory for chip operation and must be independent, free running, and jitter free.
2.1.1
Reset Operation
A reset operation initializes the status and state machines for the LOS, AIS and QRSS blocks. Writing a 1 to the bit CR2.RESET commands a reset which clears all registers to 0. Allow 32 ms for the device to settle.
2.2
2.2.1
Transmitter
Transmit Digital Data Interface
Input data for transmission onto the line is clocked serially into the device at the TCLK rate. TPOS and TNEG are the bipolar data inputs. In Unipolar mode, the TDATA pin accepts unipolar data. Input data may pass through either the Jitter Attenuator or B8ZS/HDB3 encoder or both. Setting CR1.ENCENB = 1 enables B8ZS/HDB3 encoding. With zero suppression enabled, Control Register #1 (CR1) bits EC1 through EC3 determine the coding scheme as listed in Table 8 on page 25. TCLK supplies input synchronization. See the Figure 14 on page 37 for the transmit timing requirements for TCLK and the Master Clock (MCLK).
Datasheet
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LXT351 -- T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation
2.2.2
Transmit Monitoring
The transmitter includes a short circuit limiter that limits the current sourced into a low impedance load. The limiter automatically resets when the load current drops below the limit. The current is determined by the interface circuitry (total resistance on transmit side). The Performance Status Register (PSR) flags open circuits in bit PSR.DFMO. A transition of DFMO can provide an interrupt, and its transition sets bit TSR.DFMO = 1. Writing a 1 in bit ICR.CDFMO clears the interrupt; leaving a 1 in the bit masks that interrupt.
2.2.3
Transmit Drivers
The transceiver transmits data as a 50% line code as shown in Figure 3. To reduce power consumption, the line driver is active only during transmission of marks, and is disabled during transmission of spaces. Biasing of the transmit DC level is on-chip.
Figure 3. 50% Duty Cycle Coding
Bit Cell 1 0 1
2.2.4
Transmit Idle Mode
Transmit Idle mode allows multiple transceivers to be connected to a single line for redundant applications. When TCLK is not present, Transmit Idle mode becomes active, and TTIP and TRING change to the high impedance state. Remote or Dual Loopback, TAOS or any internal transmit patterns temporarily disable the high impedance state.
2.2.5
Transmit Pulse Shape
As shown in Table 8 on page 25, the transmitted pulse shape is established by bits EC1 through EC3 of Control Register #1 (CR1). The transceiver produces DSX-1 pulses for short-haul T1 applications (settings from 0 dB to +6.0 dB of cable) or G.703 pulses for E1 applications. Shaped pulses are applied to the AMI line driver for transmission onto the line at TTIP and TRING. Refer to the Test Specifications section for pulse mask specifications.
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Datasheet
T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation -- LXT351
2.3
Receiver
A 1:1 transformer provides the interface to the twisted-pair line. Recovered data is output at RPOS/ RNEG (RDATA in Unipolar mode), and the recovered clock is output at RCLK. Refer to Table 28 and Table 28 on page 38 for receiver timing specifications.
2.3.1
Receive Data Recovery
The transceiver filters the equalized signal and applies it to the peak detector and data slicers. The peak detector samples the inputs and determines the maximum value of the received signal. The data slicers are set at 50% of the peak value to ensure optimum signal-to-noise performance. After processing through the data slicers, the received signal goes to the data and timing recovery section, then to the B8ZS/HDB3 decoder (if selected) and to the receive monitor. The data and timing recovery circuits provide input jitter tolerance significantly better than required by AT&T Pub 62411 and ITU G.823. See the "Test Specifications" section for details. Recovered data is routed to the Loss of Signal (LOS) Monitor and through the Alarm Indication Signal (AIS, Blue Alarm) Monitor. The jitter attenuator (JA) may be enabled or disabled in the receive data path or the transmit path. Received data may be routed to either the B8ZS or HDB3 decoder or neither. Finally, the device may send the digital data to the framer as either unipolar or bipolar data. When transmitting unipolar data to the framer, the device reports reception of bipolar violations by driving the BPV pin High. During E1 operation, the device can report HDB3 code violations and Zero Substitution Violations on the BPV pin.
2.4
Jitter Attenuation
A Jitter Attenuation Loop (JAL) with an Elastic Store (ES) provides jitter attenuation as shown in the Test Specifications section. The JAL requires no special circuitry, such as an external quartz crystal or high-frequency clock (higher than the line rate). Its timing reference is MCLK. Bit CR1.JASEL0 enables or disables the JA circuit. With bit CR1.JASEL0 = 1, bit CR1.JASEL1 controls the JA circuit placement (see Table 7 on page 25). The ES can be either a 32 x 2-bit or 64 x 2-bit register depending on the value of bit CR3.ES64 (see Table 10 on page 26.) The device clocks data into the ES using either TCLK or RCLK depending on whether the JA circuitry is in the transmit or receive data path, respectively. Data is shifted out of the elastic store using the dejittered clock from the JAL. When the FIFO is within two bits of overflowing or underflowing, the ES adjusts the output clock by 1/8 of a bit period. The ES produces an average delay of 16 bits (or 32 bits, with the 64-bit ES option selected) in the associated data path. When the Jitter Attenuator is in the receive path, the output RCLK transitions smoothly to MCLK in the event of a LOS condition. The Transition Status Register bits TSR.ESOVR and TSR.ESUNF indicate an elastic store overflow or underflow, respectively. Note that these are sticky bits that once set to 1, remain set until the host reads the register. The ES can also provide a maskable interrupt on either overflow or underflow.
Datasheet
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LXT351 -- T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation
2.5
Diagnostic Mode Operation
The LXT351 offers multiple diagnostic modes as listed in Table 4. The diagnostic modes are selected by setting the appropriate register bits as described in the following paragraphs.
2.5.1
2.5.1.1
Loopback Modes
Local Loopback
See Figure 4 and Figure 5. Local loopback is selected by setting CR2.ELLOOP to 1. LLOOP inhibits the receiver circuits. The transmit clock and data inputs (TCLK and TPOS/TNEG or TDATA) loop back through the jitter attenuator (if enabled) and show up at RCLK and RPOS/ RNEG or RDATA. Note that during LLOOP, the JASEL input is strictly an Enable/Disable control; it does not affect the placement of the JAL. If JA is enabled, it is active in the loopback circuit. If JA is bypassed, it is not active in the loopback circuit. The transmitter circuits are unaffected by LLOOP. LXT351 transmits the TPOS/TNEG or TDATA inputs (or a stream of 1s if TAOS is asserted) normally. When used in this mode, the transceiver can function as a stand-alone jitter attenuator.
Figure 4. Local Loopback
Table 4.
Diagnostic Mode Summary
Diagnostic Mode Loopback Modes Local Loopback (LLOOP) Analog Loopback (ALOOP) Remote Loopback (RLOOP) Dual Loopback (DLOOP) No No No No Interrupt Maskable
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Datasheet
T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation -- LXT351
Table 4.
Diagnostic Mode Summary
Diagnostic Mode Internal Data Pattern Generation Transmit All Ones (TAOS) Quasi-Random Signal Source (QRSS) Error Insertion and Detection Bipolar Violation Insertion (INSBPV) Logic Error Insertion (INSLER) Bipolar Violation Detection (BPV) HDB3 Code Violation Detection (CODEV) HDB3 Zero violation Detection (ZEROV) Alarm Condition Monitoring Receive Loss of Signal (LOS) Monitoring Receive Alarm Indication Signal (AIS) Monitoring Transmit Driver Failure Monitoring Open (DFMO) Elastic Store Overflow and Underflow Monitoring Built-In Self Test (BIST) Yes Yes Yes Yes Yes No No No No No No Yes Interrupt Maskable
Figure 5. TAOS with LLOOP
Datasheet
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LXT351 -- T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation
2.5.1.2
Analog Loopback
See Figure 6. Analog loopback (ALOOP) exercises the maximum number of functional blocks. ALOOP operation disconnects the RTIP/RRING inputs from the line and routes the transmit outputs back into the receive inputs. This tests the encoders/decoders, jitter attenuator, transmitter, receiver and timing recovery sections. Writing a 1 to bit CR2.EALOOP enables the ALOOP mode. Note that ALOOP will override all other loopback modes.
Figure 6. Analog Loopback
2.5.1.3
Remote Loopback
See Figure 7. In Remote loopback (RLOOP) mode, the device ignores the transmit data and clock inputs (TCLK and TPOS/TNEG or TDATA), and bypasses the in-line encoders/decoders. The RPOS/RNEG or RDATA outputs loop back through the transmit circuits to TTIP and TRING at the RCLK frequency. The RLOOP command does not affect the receiver circuits which continue to output the RCLK and RPOS/RNEG or RDATA signals received from the twisted-pair line. RLOOP is selected by writing a 1 to bit CR2.ERLOOP.
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Datasheet
T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation -- LXT351
Figure 7. Remote Loopback
2.5.1.4
Dual Loopback
See Figure 8. To select Dual loopback (DLOOP) set bits CR2.ERLOOP and CR2.ELLOOP to 1. In DLOOP mode, the transmit clock and data inputs (TCLK and TPOS/TNEG or TDATA) loop back through the Jitter Attenuator (unless disabled) to RCLK and RPOS/RNEG or RDATA. The data and clock recovered from the twisted-pair line loop back through the transmit circuits to TTIP and TRING without jitter attenuation.
Figure 8. Dual Loopback
2.5.2
2.5.2.1
Internal Pattern Generation
Transmit All Ones
See Figure 9. In Transmit All Ones (TAOS) mode, the transceiver ignores the TPOS and TNEG inputs and transmits a continuous stream of 1s at the TCLK frequency. (With no TCLK, the TAOS output clock is MCLK.) This can be used as the Alarm Indication Signal (AIS-also called the Blue Alarm). TAOS is commanded by writing a 1 to bit CR2.ETAOS. Both TAOS and Local loopback can occur simultaneously as shown in Figure 4, however, Remote loopback inhibits TAOS. When both TAOS and LLOOP are active, TCLK and TPOS/TNEG loop back to RCLK and RPOS/RNEG through the jitter attenuator (if enabled), and an all ones pattern goes to TTIP/TRING.
Datasheet
19
LXT351 -- T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation
Figure 9. TAOS Data Path
2.5.2.2
Quasi-Random Signal Source (QRSS)
See Figure 10. For T1 operation, the Quasi-Random Signal Source (QRSS) is a 220-1 pseudorandom bit sequence (PRBS) with no more than 14 consecutive zeros. For E1 operation, QRSS is 215-1 PRBS with inverted output. Setting bits CR2.EPAT0 = 0 and CR2.EPAT1 = 1 enables this function. The QRSS pattern is normally locked to TCLK; but if there is no TCLK, MCLK is the clock source. Bellcore Pub 62411 defines the T1 QRSS transmit format and ITU G.703 defines the E1 format.
Figure 10. QRSS Mode
* If Enabled
INT*
With QRSS transmission enabled, it is possible to insert a logic error into the transmit data stream by causing a Low-to-High transition on INSLER. However, if no logic or bit errors are to be inserted into the QRSS pattern, INSLER must remain Low. Logic Error insertion waits until the next bit if the current bit is "jammed". When there are more than 14 consecutive 0s, the output is jammed to a 1. Furthermore, a bipolar violation in the QRSS pattern is possible by causing a Low-to-High transition on the INSBPV pin, regardless of whether the device is in Bipolar or Unipolar mode. Choosing QRSS mode also enables the QRSS Pattern Detection in the receive path. The QRSS pattern is synchronized when there are fewer than four errors in 128 bits. The PSR.QRSS bit provides an indication of QRSS pattern synchronization. This bit goes Low when no QRSS pattern detected (i.e., when there are more than four errors in 128 bits). The TQRSS bit in the Transition Status Register indicates that QRSS status has changed since the last QRSS Interrupt Clear command. The LXT351 can generate an interrupt to indicate that QRSS detection has occurred, or that synchronization is lost. The interrupt is enabled when ICR.CQRSS = 0.
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T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation -- LXT351
2.5.3
2.5.3.1
Error Insertion and Detection
Bipolar Violation Insertion (INSBPV)
Bipolar violation insertion is available In Unipolar mode. Choosing Unipolar mode configures the INSBPV pin. To insert bipolar violation (BPV), a Low-to-High transition on the INSBPV is required. Sampling occurs on the falling edge of TCLK. When INSBPV goes High a BPV is inserted on the next available mark except in the four following situations:
* Zero suppression (HDB3 or B8ZS) is not violated * If LLOOP and TAOS are both active, the BPV is looped back to RNEG/BPV indicator and the
line driver transmits all ones with no violation
* BPV insertion is disabled with RLOOP active
With the LXT351 configured to transmit internally generated data patterns, a BPV can be inserted into the transmit pattern regardless of whether the device is in the Unipolar or Bipolar mode of operation.
2.5.3.2
Logic Error Insertion (INSLER)
When configured to transmit internally generated data patterns, a logic error is inserted into the transmit data pattern when the INSLER pin transitions Low-to-High. Note that in QRSS mode, there is no logic error insertion on a jammed bit (i.e., a bit forced to one to suppress transmission of more than 14 consecutive zeros). The transceiver routes data patterns the same way it routes data applied to TPOS/TNEG. Therefore, the inserted logic error will follow the data flow path of the active loopback mode.
2.5.3.3
Bipolar Violation Detection (BPV)
When the internal encoders/decoders are disabled or when configured in Unipolar mode, bipolar violations are reported at the BPV pin. BPV goes High for a full clock cycle to indicate receipt of a BPV. When the encoders/decoders are enabled, the LXT351 does not report bipolar violations due to the line coding scheme.
2.5.3.4
HDB3 Code Violation Detection (CODEV)
An HDB3 code violation (CODEV) occurs when two consecutive bipolar violations of the same polarity are received (refer to ITU O.161). When CODEV detection is enabled, the BPV pin goes High for a full RCLK cycle to report a CODEV violation. Note that bipolar violations and zero substitution violations will also be reported on the BPV pin if these options are enabled. HDB3 code violation detection is enabled when the HDB3 encoders/decoders are enabled. This requires that CR1.ENCENB = 1, also CR1.EC3:1 = 000, which establishes E1 operation. To select CODEV detection, set bit CR4.CODEV = 1.
2.5.3.5
HDB3 Zero Substitution Violation Detection (ZEROV)
An HDB3 ZEROV is the receipt of four or more consecutive zeros. This does not occur with correctly encoded HDB3 data unless there are transmission errors. The BPV pin goes High for a full RCLK cycle to report a ZEROV. Note that when ZEROV detection enabled, the BPV pin will also indicate received BPVs and CODEVs, if these detection options are enabled.
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LXT351 -- T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation
ZEROV detection is enabled when the HDB3 encoders/decoders are enabled. This requires CR1.ENCENB = 1, also CR1.EC3:1 = 000, which establishes E1 operation. To select ZEROV detection, set bit CR4.ZEROV = 1.
2.5.4
2.5.4.1
Alarm Condition Monitoring
Loss of Signal
The LXT351 Loss of Signal (LOS) monitor function is compatible with ITU G.775 and ETSI 300233. The receiver LOS monitor loads a digital counter at the RCLK frequency. The count increments with each received 0 and the counter resets to 0 on receipt of a 1. When the count reaches "n" 0s, bit PSR.LOS is set to `1', and the MCLK replaces the recovered clock at the RCLK output in a smooth transition. For T1 operations, the number of 0s, n = 175, and for E1 operations, n = 32. For both T1 and E1 operation, "n" can be set to 2048 by setting bit CR4.LOS2048 = 1. For T1 operation, when the received signal has 12.5% 1s (16 marks in a sliding 128-bit period, with fewer than 100 consecutive 0s), bit PSR.LOS = 0 and the recovered clock replaces MCLK at the RCLK output in another smooth transition. For E1 operation, the LOS condition is cleared when the received signal has 12.5% 1s density (four 1s in a sliding 32-bit window with fewer than 16 consecutive 0s). In E1 operation, the out-of-LOS criterion can be modified from 12.5% marks density to 32 consecutive marks by setting bit CR4.COL32CM = 1. During LOS, the device sends received data to the RPOS/RNEG pins (or RDATA in Unipolar mode). Bit PSR.LOS = 1 to indicate LOS condition, and can generate an interrupt to the host controller if so programmed.
2.5.4.2
Alarm Indication Signal Detection
The receiver detects an AIS pattern when it receives fewer than three 0s in any string of 2048 bits. The device clears the AIS condition when it receives three or more 0s in a string of 2048 bits. The AIS bit in the Performance Status Register indicates AIS detection. Whenever the AIS status changes, bit TSR.TAIS =1. Unless masked, a change of AIS status generates an interrupt.
2.5.4.3
Driver Failure Open Mode
The DFM Open (DFMO) bit is available in the Performance Status Register to indicate an open condition on the lines. DFMO can generate an INT to the host controller. The Transition Status Register bit TDFMO indicates a transition in the status of the bit. Writing a 1 to ICR.CDFMO will clear or mask the interrupt.
2.5.4.4
Elastic Store Overflow/Underflow
When the bit count in the Elastic Store (ES) is within two bits of overflowing or underflowing the ES adjusts the output clock by 1/8 of a bit period. The ES provides an indication of overflow and underflow via bits TRS.ESOVR and TSR.ESUNF. These are sticky bits and will stay set to 1 until the host controller reads the register. These interrupts can be cleared or masked by writing a 1 to the bits ICR.CESO and ICR.CESU, respectively.
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T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation -- LXT351
2.5.4.5
Built-In Self Test
LXT351 provides a Built-In Self Test (BIST) capability. The BIST exercises the internal circuits by providing an internal QRSS pattern, running it through the encoders and the transmit drivers then looping it back through the receive equalizer, jitter attenuator and decoders to the QRSS pattern detection circuitry. If all the blocks in this data path function correctly, the receive pattern detector locks onto the pattern. It then pulls INT Low and sets the following bits:
* TSR.TQRSS = 1 * PSR.QRSS = 1 * PSR.BIST = 1
Note that during BIST, the TPOS/TNEG inputs must remain at logic level = 0 The most reliable test will result when a separate TCLK and MCLK are applied.
2.6
Parallel Microprocessor Interface
The LXT351 multiplexed address/data bus and timing/control signals are compatible with both the Intel and Motorola microprocessors. See Figure 16 and Figure 17 for the I/O timing diagram for each bus. The LXT351 detects and distinguishes between Intel and Motorola timing and then automatically selects the appropriate bus timing. The maximum recommended processor speed for an Intel device is 20 MHz; for a Motorola device, 16.78 MHz. See "Test Specifications" on page 33 for microprocessor interface timing details. The LXT351 contains five read/write and two read-only registers for control and status purposes. Table 6 on page 24 is a summary of the registers. Table 7 through Table 14 identify and explain the function of the register bits.
2.6.1
Interrupt Handling
The LXT351 provides a latched interrupt output pin (INT). When enabled, a change in any of the Performance Status Register bits will generate an interrupt. An interrupt can also be generated when the elastic store overflows (TSR.ESOVR) or underflows (TSR.ESUNF). When an interrupt occurs, the INT output pin is pulled Low. Note that the output stage of the INT pin has internal pull-down only. Therefore, each device that shares the INT line requires an external pull-up resistor. The interrupt is cleared when the interrupt condition no longer exists, and the host processor writes a 1 to the respective interrupt causing bit(s) in the Interrupt Clear Register (ICR). Leaving a 1 in any of the ICR bits masks that interrupt. To re-enable an interrupt bit, write a 0.
Datasheet
23
LXT351 -- T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation
3.0
Register Definitions
The LXT351 contains five read/write and two read-only registers that are accessible via the parallel port. Table 5 lists the LXT351 register addresses. Only bits A6 through A1 of the address byte are valid (the address decoder ignores bits A7 and A0) while A0 functions as the read/write (R/W) bit. Table 6 identifies the name of each register bit. Table 7 through Table 14 describe the function of the bits in each register. Note that upon power-up or reset, all registers are cleared to 0.
Table 5.
Register Addresses
Register Name Control #1 Control #2 Control #3 Interrupt Clear Transition Status Performance Status Control #4 Abbr CR1 CR2 CR3 ICR TSR PSR CR4 Address1, 2 A7 - A1 x010000 x010001 x010010 x010011 x010100 x010101 x010111
1. x = don't care 2. Address A0 is the read/write (R/W) bit.
Table 6.
Register and Bit Summary
Bit Type CR1 CR2 CR3 ICR TSR PSR CR4 R/W R/W R/W R/W R R R/W 7 JASEL1 RESET JA6HZ CESU ESUNF reserved1 reserved1 6 JASEL0 EPAT1 reserved CESO ESOVR BIST reserved1
1
Register Name Control #1 Control #2 Control #3 Interrupt Clear Transition Status Performance Status Control #4 5 ENCENB EPAT0 SBIST CDFMO TDFMO DFMO reserved1 4 UNIENB ETAOS
3 reserved reserved reserved
1 1 1
2 EC3 EALOOP ES64 CAIS TAIS AIS LOS2048
1 EC2 ELLOOP ESCEN reserved2 reserved1 reserved1 ZEROV
0 EC1 ERLOOP ESJAM CLOS TLOS LOS CODEV
EQZMON reserved2 reserved1 reserved1 reserved1
CQRSS TQRSS QRSS COL32CM
1. In writable registers, bits labeled reserved should be set to 0 (except as in note 2 below) for normal operation and ignored in read only registers. 2. Write a 1 to this bit for normal operation.
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T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation -- LXT351
Table 7.
Bit 0 1 2 3 4 Name EC1 EC2 EC3 UNIENB
Control Register #1 Read/Write, Address (A7-A0) = x010000x
Jitter Attenuator Function JASEL0 1 Sets mode (T1 or E1) and equalizer (see Table 8 below for control codes). Reserved, set this bit to 0, ignore when reading. 1 = Enable Unipolar I/O mode and allow insertion/detection of BPVs. 0 = Enable Bipolar I/O mode 1 = Enable B8ZS/HDB3 encoders/decoders and force Unipolar I/O mode. 0 = Disable B8ZS/HDB3 encoders/decoders 1 0 JASEL1 0 1 X Position Transmit Receive Disabled
5 6 7
ENCENB JASEL0 JASEL1
Select jitter attenuation circuitry position in data path or disables the JA. See right hand section of table for codes.
N
Table 8.
EC3 0 0 1 1 1 1 EC2 0 1 0 0 1 1
Equalizer Control Input Settings
EC1 0 1 0 1 0 1 Function E1 T1 T1 T1 T1 T1 Pulse ITU Rec G.703 0-133 ft / 0.6 dB 133-266 ft / 1.2 dB 266-399 ft / 1.8 dB 399-533 ft / 2.4 dB 533-655 ft / 3.0 dB Cable 75 Coax/120 TP 100 TP 100 TP 100 TP 100 TP 100 TP Coding1 HDB3 B8ZS B8ZS B8ZS B8ZS B8ZS
1. When enabled.
Table 9.
Bit Name
Control Register #2 Read/Write, Address (A7-A0) = x010001x
Pattern Function EPAT0 EPAT1 0 1 0 1 Selected Transmit TPOS/TNEG Detect and transmit QRSS In-band Loop Up Code 00001 In-band Loop Down Code 001 1 = Enable Remote loopback mode 0 = Disable Remote loopback mode 1 = Enable Local loopback mode 0 = Disable Local loopback mode 1 = Enable Analog loopback mode 0 = Disable Analog loopback mode Reserved, set to 0, ignore when reading.
0 1 2 3
ERLOOP1 ELLOOP1 EALOOP -
0 0 1 1
1. To enable Dual loopback (DLOOP), set both ERLOOP = 1 and ELLOOP = 1.
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LXT351 -- T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation
Table 9.
Bit Name
Control Register #2 Read/Write, Address (A7-A0) = x010001x
Pattern Function EPAT0 EPAT1 Selected 1 = Enable Transmit All Ones 0 = Disable Transmit All Ones Selects internal data pattern transmission. See right hand section of table for codes.
4 5 6 7
ETAOS EPAT0 EPAT1 RESET
N
1 = Reset device states and clear all registers. 0 = Reset complete.
1. To enable Dual loopback (DLOOP), set both ERLOOP = 1 and ELLOOP = 1.
Table 10. Control Register #3 Read/Write, Address (A7-A0) = x010010x
Bit 0 1 2 3 4 5 6 7 Name ESJAM ESCEN ES64 EQZMON SBIST JA6HZ Description 1 = Disable jamming of Elastic Store read out clock (1/8 bit-time adjustment for over/underflow). 0 = Enable jamming of Elastic Store read out clock 1 = Center ES pointer for a difference of 16 or 32, depending on depth (clears automatically). 0 = Centering completed 1 = Set elastic store depth to 64 bits. 0 = Set elastic store depth to 32 bits. Reserved. Set to 0 for normal operation. 1 = Configure receiver equalizer for monitor mode application (DSX-1 monitor). 0 = Configure receiver equalizer for normal mode application 1 = Start Built-In Self Test. 0 = Built-In Self Test complete. Reserved. Set to 0 for normal operation. 1 = Set bandwidth of jitter attenuation loop to 6 Hz. 0 = Set bandwidth of jitter attenuation loop to 3 Hz.
Table 11. Interrupt Clear Register Read/Write, Address (A7-A0) = x010011x
Bit 0 1 2 3 4 Name CLOS CAIS CQRSS 1 = Clear/Mask Loss of Signal interrupt. 0 = Enable Loss of Signal interrupt. Reserved. Set to 1 for normal operation. 1 = Clear/Mask Alarm Indication Signal interrupt. 0 = Enable Alarm Indication Signal interrupt. 1 = Clear/Mask Quasi-Random Signal Source interrupt. 0 = Enable Quasi-Random Signal Source interrupt. Reserved. Set to 1 for normal operation. Function1
1. Leaving a 1 of in any of these bits masks the associated interrupt.
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T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation -- LXT351
Table 11. Interrupt Clear Register Read/Write, Address (A7-A0) = x010011x
Bit 5 6 7 Name CDFMO CESO CESU Function1 1 = Clear/Mask Driver Failure Monitor Open interrupt. 0 = Enable Driver Failure Monitor Open interrupt. 1 = Clear/Mask Elastic Store Overflow interrupt. 0 = Enable Elastic Store Overflow interrupt. 1 = Clear/Mask Elastic Store Underflow interrupt. 0 = Enable Elastic Store Underflow interrupt.
1. Leaving a 1 of in any of these bits masks the associated interrupt.
Table 12. Transition Status Register Read Only, Address (A7-A0) = x010100x
Bit 0 1 2 3 4 5 6 7 Name TLOS TAIS TQRSS TDFMO ESOVR ESUNF Function 1 = Loss of Signal (LOS) has changed since last clear LOS interrupt occurred. 0 = No change in status. Reserved. Ignore. 1 = AIS has changed since last clear AIS interrupt occurred. 0 = No change in status. 1 = QRSS has changed since last clear QRSS interrupt occurred1. 0 = No change in status. Reserved. Ignore. 1 = DFMO has changed since last clear DFMS interrupt occurred. 0 = No change in status. 1 = ES overflow status sticky bit2. 0 = No change in status. 1 = ES underflow status sticky bit2. 0 = No change in status.
1. A QRSS transition indicates receive QRSS pattern sync or loss. A simple error in QRSS pattern is not reported as a transition. 2. Tripping the overflow or underflow indicator in the ES sets the ESOVR/ESUNF status bit(s). Reading the Transition Status Register clears these bits. Setting CESO and CESU in the Interrupt Clear Register masks these interrupts.
Table 13. Performance Status Register Read Only, Address (A7-A0) = x010101x
Bit 0 1 2 3 4 Name LOS AIS QRSS 1 = Loss of Signal occurred. 0 = Loss of Signal did not occur. Reserved. Ignore. 1 = Alarm Indicator Signal detected. 0 = Alarm Indicator Signal not detected. 1 = Quasi-Random Signal Source pattern detected. 0 = Quasi-Random Signal Source pattern not detected. Reserved. Ignore. Function
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LXT351 -- T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation
Table 13. Performance Status Register Read Only, Address (A7-A0) = x010101x
Bit 5 6 7 Name DFMO BIST 1 = Driver Failure Monitor Open detected. 0 = Driver Failure Monitor Open not detected. 1 = Built-In Self Test passed. 0 = Built-In Self Test did not pass (or was not run). Reserved. Ignore. Function
Table 14. Control Register #4 Read/Write, Address (A7-A0) = x010111x
Bit Name Function 1 = Enable detection of HDB3 code violations at the BPV pin along with bipolar violations and Zero Substitution Violations (if enabled). 0 = Disable detection of HDB3 code violations 1 ZEROV 1 = Enable detection of HDB3 Zero Substitution Violations (four consecutive zeros). Note that Zero Substitution Violations are reported at the BPV pin. 0 = Disable detection of HDB3 Zero Substitution Violations. 1 = Set LOS detection threshold to 2048 consecutive zeros. 2 LOS2048 0 = Set LOS detection threshold to 32 consecutive zeros (for E1 operation) or to 175 consecutive zeros (for T1 operation). 1 = Set LOS clear condition criterion to receipt of 32 consecutive marks (E1 operation). 0 = Set LOS clear condition criterion to 12.5% mark density (E1 operation). Reserved. Set to 0 for normal operation, ignore when reading Reserved. Set to 0 for normal operation, ignore when reading Reserved. Set to 0 for normal operation, ignore when reading Reserved. Set to 0 for normal operation, ignore when reading
0
CODEV
3 4 5 6 7
COL32CM -
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T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation -- LXT351
4.0
4.1
Application Information
Transmit Return Loss
Table 15 shows the specification for transmit return loss in E1 applications. The G.703/CH PTT specification is a Swiss Telecommunications Ministry specification. Table 16 and Table 17 show the transmit return loss values for E1 and T1 applications.
4.2
Transformer Data
Specifications for transformers are listed in Table 18. A list of transformers recommended for use with the LXT351 are specified in Table 19.
4.3
Application Circuit
Figure 11 shows a typical LXT351 application.
4.4
Line Protection
On the receive side, 1 k series resistors protect the receiver against current surges coupled into the device. Due to the high receiver impedance (40 k typical) the resistors do not affect the receiver sensitivity. On the transmit side, Schottky diodes D1-D4 protect the output driver. While not mandatory for normal operation, these protection elements are strongly recommended to improve the design robustness
Table 15. E1 Transmit Return Loss Requirements
Return Loss Frequency Band ETS 300 166 51-102 kHz 102-2048 kHz 2048 - 3072 kHz 6 dB 8 dB 8 dB G.703/CH PTT 8 dB 14 dB 10 dB
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LXT351 -- T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation
Table 16. Transmit Return Loss (2.048 Mbps)
EC3-1 Xfrmr/Rt RL () CL (pF) 0 75 1:2/ 9.1 000 1:2.3/9.1 120 470 0 120 470 16 13 13 470 0 16 12 Return Loss (dB) 14
Table 17. Transmit Return Loss (1.544 Mbps)
EC3-1 Xfrmr/Rt 1:2/ 9.1 0112 1:1.151/ 0.0 100 470 2 RL () CL (pF) 0 100 470 0 17 2 Return Loss (dB) 16
1. A 1:1.15 transmit transformer keeps the total transceiver power dissipation at a low level, a 0.47 F DC blocking capacitor must be placed on TTIP or TRING. 2. Refer to Table 8.
Table 18. Transformer Specifications
Tx/Rx Frequency MHz Turns Ratio Primary Inductance H (minimum) 600 600 600 600 Leakage Inductance H (max) 0.80 0.80 0.80 1.10 Interwinding Capacitance pF (max) 60 60 60 60 DCR (maximum) 0.90 pri 1.70 sec 0.70 pri 1.20 sec 1.0 pri 1.70 sec 1.10 pri 1.10 sec Dielectric1 Breakdown V (minimum) 1500 VRMS 1500 VRMS2 (3000 VRMS) 1500 VRMS2 (3000 VRMS) 1500 VRMS2 (3000 VRMS)
1.544 Tx 2.048 1.544/2.048 Rx 1.544/2.048
1:1.15 1:2.3 1:2 1:1
1. Some ETSI applications may require a 2.3 kV dielectric breakdown voltage. 2. Some applications require transformers to guarantee performance in extended temperature range (-40 to +85 C) ETSI applications require a dielectric breakdown voltage of 3000 VRMS.
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T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation -- LXT351
Table 19. Recommended Transformers
Tx/Rx Turns Ratio Part Number PE-65388 Pulse Engineering 1:1.15 PE-65770 16Z5952 PE-65351 Pulse Engineering PE-65771 0553-5006-IC 66Z-1308 671-5832 Tx 1:2 67127370 Schott Corp 67130850 TD61-1205D TG26-1205NI TG48-1205NI 16Z5946 1:2.3 PE-65558 FE 8006-155 671-5792 PE-64936 Pulse Engineering Rx 1:1 PE-65778 67130840 Schott Corp 67109510 TD61-1205D HALO (combination Tx/Rx set) HALO (combination Tx/Rx set) HALO (surface mount dual transformer 1CT:2CT & 1CT:2CT) HALO (surface mount dual transformer 1CT:2CT & 1:1) Vitec Pulse Engineering Fil-Mag Midcom Bell-Fuse Fil-Mag Midcom Vitec Manufacturer
4.4.1
LXT351 Application Circuit
Figure 11 shows a typical application using the LXT351. See Table 16 and Table 17 to select the transformers (T1 and T2), resistors (Rt and RL) and capacitors (CL) needed for this application. Note: If the application includes surge protection, such as a varistor or sidactor on the TTIP/TRING lines, it may also require reducing the value of the capacitor CL or eliminating it completely.
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LXT351 -- T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation
Figure 11. Typical T1/E1 LXT351 Application
VCC 22 k 2.048 MHz/ 1.544 MHz MCLK INT ALE/AS TCLK TPOS TCLK TPOS TNEG RCLK RPOS RNEG RD/DS WR/R/W CS P (Intel or Motorola)
T1/E1 TNEG Framer
RPOS
RCLK
LXT351
AD0-7 TTIP 1:21 Rt1 CL1
RNEG
TVCC VCC 0.1 F 68 F TGND GND RRING TRING RTIP
Rt1
RL2
1:1
NOTES: 1. See Table 16 and Table 17 for CL, Rt and Transformer selection. 2. RL = 100 for T1 RL = 120 for E1/120 twisted pair RL = 75 for E1/75 coax
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T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation -- LXT351
5.0
Note:
Test Specifications
Table 20 through Table 31 and Figure 12 through Figure 21 represent the performance specifications of the LXT350/351 and are guaranteed by test except, where noted, by design. The minimum and maximum values listed in Table 22 through Table 31 are guaranteed over the recommended operating conditions specified in Table 21.
Table 20. Absolute Maximum Ratings
Parameter DC supply (reference to GND) Input voltage, any pin Input current, any pin Storage Temperature
1 2
Sym VCC, TVCC VIN IIN TSTG
Min - GND - 0.3 V - 10 -65
Max 6.0 VCC + 0.3 V 10 150
Unit V V mA C
Caution: Exceeding these values may cause permanent damage. Caution: Functional operation under these conditions is not implied. Caution: Exposure to maximum rating conditions for extended periods may affect device reliability. 1. TVCC and VCC must not differ by more than 0.3 V during operation. TGND and GND must not differ by more than 0.3 V during operation. 2. Transient currents of up to 100 mA will not cause SCR latch-up. TTIP, TRING, TVCC, and TGND can withstand continuous currents of up to 100 mA.
Table 21. Recommended Operating Conditions
Parameter DC supply
2
Sym VCC,TVCC TA PD T1
Min 4.75 - 40 - - - -
Typ1 5.0 25 310 225 275 215
Max 5.25 85 380 295 330 270
Unit V C mW mW mW mW
Test Conditions
Ambient operating temperature
100% mark density 50% mark density 100% mark density 50% mark density
Total power dissipation3 E1
PD PD PD
1. Typical figures are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. TVCC and VCC must not differ by more than 0.3 V. 3. Power dissipation while driving 75 load over operating range for T1 operation or 60 load for E1 operation. Includes power dissipation on device and load. Digital levels are within 10% of the supply rails and digital outputs driving a 50 pF capacitive load.
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LXT351 -- T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation
Table 22. DC Electrical Characteristics
Parameter Digital I/O pins High level input voltage 2 (pins 1-5, 9-12, 17, 23-28)3 Low level input voltage
2
Sym
Min
Typ1
Max
Unit
Test Conditions
VIH VIL VOH VOL ILL
2.0 - 2.4 - -
- - - - -
- 0.8 - 0.4 10
V V V V IOUT = -400 A IOUT = 1.6 mA
(pins 1-5, 9-12, 17, 23-28)
2
3
High level output voltage (pins 6-8, 10, 11,23, 28)
3
Low level output voltage 2 (pins 6-8, 10, 11,23, 28)3 Input leakage current
A
1. Typical figures are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. Output drivers will output CMOS logic levels into CMOS loads. 3. Listed pins are for the PLCC package. Refer to "Pin Assignments and Signal Descriptions" on page 8 for the 44-pin QFP package.
Table 23. Analog Characteristics
Parameter Recommended output load on TTIP/TRING T1 AMI output pulse amplitudes E1 10 Hz - 8 kHz Jitter added by the transmitter2 8 kHz - 40 kHz
3 3
Min 50 2.4 2.7 - - - - 0 160 - 0.4 138 0.2 37 - - - 51 kHz - 102 kHz3 20 20
3
Typ1 - 3.0 3.0 - - - - - 175 32 - - - - 3 3 40 22 28 30
Max 200 3.6 3.3 0.02 0.025 0.025 0.05 18 190 - - - - - - - - - - -
Unit
Test Conditions
V V UI UI UI UI dB - - UI UI UI UI Hz 0 dB line AT&T Pub 62411 0 dB line ITU (G.823) selectable in data port @ 1024 kHz 1.431 RL = 100 RL = 120
10 Hz - 40 kHz3 Broad Band
Receiver sensitivity Allowable consecutive zeros before LOS (T1) Allowable consecutive zeros before LOS (E1) 10 kHz - 100 kHz Input jitter tolerance (T1) 1 Hz Input jitter tolerance (E1) Jitter attenuation curve corner frequency 4 Driver output impedance Receiver input impedance
3
10 kHz - 100 kHz 1 Hz3
k dB dB dB RTIP to RRING
Receive return loss (E1)
102 kHz - 2.048 MHz3 2.048 MHz - 3.072 MHz
25
1. 2. 3. 4.
Typical figures are at 25 C and are for design aid only; not guaranteed and not subject to production testing. Input signal to TCLK is jitter-free. The Jitter Attenuator is in the receive path or disabled. Guaranteed by characterization; not subject to production testing. Circuit attenuates jitter at 20 dB/decade above the corner frequency.
34
Datasheet
T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation -- LXT351
Figure 12. 2.048 Mbps E1 Pulse (See Table 24)
478 ns
V = 100%
10% 10%
20%
345 ns 20%
NOMINAL PULSE 50%
434 ns 390 ns
10% 10%
0%
20%
870 ns
Table 24. 2.048 Mbps E1 Pulse Mask Specifications
Parameter Test load impedance Nominal peak mark voltage Nominal peak space voltage Nominal pulse width Ratio of positive and negative pulse amplitudes at center of pulse Ratio of positive and negative pulse amplitudes at nominal half amplitude TPW 120 3.0 0 0.30 244 95-105 95-105 Coax 75 2.37 0 0.237 244 95-105 95-105 Unit
10% 10%
V V ns % %
Datasheet
35
LXT351 -- T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation
Figure 13. 1.544 Mbps T1 Pulse, DSX-1 (See Table 25)
1.5
Normalized Amplitude
1.0
0.5 -0.5 0.0 Time
(in Unit Intervals)
0.5
1.0
1.5
-0.5
0
Table 25. 1.544 Mbps T1, DSX-1 Pulse Mask Corner Point Specifications
DSX-1 Template (per ANSI T1. 102-1993) Minimum Curve Time (UI) -0.77 -0.23 -0.23 -0.15 0.0 0.15 0.23 0.23 0.46 0.66 0.93 1.16 Amplitude -0.05 -0.05 0.50 0.95 0.95 0.90 0.50 -0.45 -0.45 -0.20 -0.05 -0.05 Time (UI) -0.77 -0.39 -0.27 -0.27 -0.12 0.0 0.27 0.35 0.93 1.16 Maximum Curve Amplitude 0.05 0.05 0.80 1.15 1.15 1.05 1.05 -0.07 0.05 0.05 -
36
Datasheet
T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation -- LXT351
Table 26. Master and Transmit Clock Timing Characteristics for T1 Operation (See Figure 14)
Parameter Master clock frequency Master clock tolerance Master clock duty cycle Transmit clock frequency Transmit clock tolerance Transmit clock duty cycle TPOS/TNEG to TCLK setup time TCLK to TPOS/TNEG hold time Sym MCLK MCLKt MCLKd TCLK TCLKt TCLKd tSUT tHT Min - - 40 - - 10 50 50 Typ1 1.544 32 - 1.544 - - - - Max - - 60 - 100 90 - - Unit MHz ppm % MHz ppm % ns ns Notes must be supplied
1. Typical figures are at 25 C and are for design aid only; not guaranteed and not subject to production testing.
Table 27. Master and Transmit Clock Timing Characteristics for E1 Operation (See Figure 14)
Parameter Master clock frequency Master clock tolerance Master clock duty cycle Transmit clock frequency Transmit clock tolerance Transmit clock duty cycle TPOS/TNEG to TCLK setup time TCLK to TPOS/TNEG hold time Sym MCLK MCLKt MCLKd TCLK TCLKt TCLKd tSUT tHT Min - - 40 - - 10 50 50 Typ1 2.048 32 - 2.048 - - - - Max - - 60 - 100 90 - - Unit MHz ppm % MHz ppm % ns ns Notes must be supplied
1. Typical figures are at 25 C and are for design aid only; not guaranteed and not subject to production testing.
Figure 14. Transmit Clock Timing
Datasheet
37
LXT351 -- T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation
Table 28. Receive Timing Characteristics for T1 Operation (See Figure 15)
Parameter Receive clock duty cycle 2, 3 Receive clock pulse width
2, 3
Sym RLCKd tPW tPWH
Min 40 - - 260 - -
Typ1 50 648 324 324 274 274
Max 60 - - 388 - -
Unit % ns ns ns ns ns
Receive clock pulse width High Receive clock pulse width Low
1,3
tPWL tSUR tHR
RPOS/RNEG to RCLK rise time RCLK rise to RPOS/RNEG hold time
1. Typical s are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. RCLK duty cycle widths will vary according to extent of received pulse jitter displacement. Max and Min RCLK duty cycles are for worst case jitter conditions. 3. Worst case conditions guaranteed by design only.
Table 29. Receive Timing Characteristics for E1 Operation (See Figure 15)
Parameter Receive clock duty cycle 2, 3 Receive clock pulse width 2, 3 Receive clock pulse width High Receive clock pulse width Low
1,3
Sym RLCKd tPW tPWH tPWL tSUR tHR
Min 40 - - 195 - -
Typ1 50 488 244 244 194 194
Max 60 - - 293 - -
Unit % ns ns ns ns ns
RPOS/RNEG to RCLK rise time RCLK rise to RPOS/RNEG hold time
1. Typical figures are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. RCLK duty cycle widths will vary according to extent of received pulse jitter displacement. Max and Min. RCLK duty cycles are for worst case jitter conditions (0.4 UI clock displacement for 1.544 MHz). 3. Worst case conditions guaranteed by design only.
Figure 15. Receive Clock Timing
38
Datasheet
T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation -- LXT351
Table 30. 20 MHz Intel Bus Parallel I/O Timing Characteristics (See Figure 16)
Parameter ALE pulse width Address valid to ALE falling edge ALE falling edge to address hold time ALE falling edge to RD falling edge ALE falling edge to WR falling edge CS falling edge to RD falling edge CS falling edge to WR falling edge RD Low pulse width RD falling edge to data valid Data hold time after RD rising edge RD rising edge to ALE rising edge RD rising edge to address valid CS Low hold time after RD rising edge WR Low pulse width Data setup time before WR rising edge Data hold time after WR rising edge WR rising edge to ALE rising edge CS Low hold time after WR rising edge Sym TLHLL TAVLL TLLAX TLLRL TLLWL TCLRL TCLWL TRLRH TRLDV TRHDX TRHLH TRHAV TRHCH TWLWH TDVWH TWHDX TWHLH TWHCH Min 35 10 10 10 10 10 10 95 10 5 15 35 0 95 40 30 15 15 Max - - - - - - - - 55 35 - - - - - - - - Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Test Conditions
Datasheet
39
LXT351 -- T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation
Figure 16. Intel Address/Data Bus Timing
0ns
50ns
100ns
150ns
200ns
CS
TCLWL TCLRL
TWHCH TRHCH
TLHLL TLLAX ALE TAVLL
RD
TLLRL TLLWL
TRHLH TWHLH TRLRH TRLDV TRHAV TRHDX
AD0-7_R
TWLWH
WR
TDVWH
TWHDX
AD0-7_W
Table 31. 16.78 MHz Motorola Bus Parallel I/O Timing Characteristics (See Figure 17)
Parameter DS rising edge to AS rising edge AS High pulse width Address valid setup time at AS falling edge AS falling edge to Address valid hold time AS falling edge to DS falling edge CS falling edge to DS falling edge DS Low pulse width DS falling edge to data valid Data hold time after DS rising edge R/W falling edge to DS falling edge Data setup time before DS rising edge Data hold time after DS rising edge R/W Low hold time after DS rising edge CS Low hold time after DS rising edge Sym TDSHASH TASHASL TAVASL Taslax TASLDSL TCSLDSL TDSLDSH TDSLDV TDSHDX TRWLDSL TDVDSH Tdxdsh TDSHRWH TDSHCSH Min 15 35 10 10 20 10 95 10 5 10 40 30 15 15 Max - - - - - - - 55 35 - - - - - Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns Test Conditions
40
Datasheet
T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation -- LXT351
Figure 17. Motorola Address/Data Bus Timing
CS
TCSLDSL
TDSHCSH
TASHASL TAVASL
AS
TASLDSL TASLAX
TDSHASH TDSLDSH TDXDSH TDVDSH TDSHRWH
DS R/W_Read AD0-7_Read R/W_Write AD0-7_Write
TRWLDSL
TDSLDV
TDSHDX
Figure 18. Typical T1 Jitter Tolerance at 36 dB
1000 UI
Jitter
138 UI 100 UI
500 UI @ 10 Hz
LXT351 Device Typical Jitter Tolerance Loop Mode
Pub 62411
28 UI 10 UI
Dec 1990
0.6 UI @ 10 kHz 1 UI 0.4 UI .1 UI 1 Hz 10 Hz 100 Hz 1 kHz 10 kHz 100 kHz
Frequency
Datasheet
41
LXT351 -- T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation
Figure 19. Typical E1 Jitter Tolerance at 43 dB
42
Datasheet
T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation -- LXT351
Figure 20. Typical E1 Jitter Attenuation
Datasheet
43
LXT351 -- T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation
Figure 21. Typical T1 Jitter Attenuation
44
Datasheet
T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation -- LXT351
6.0
Mechanical Specifications
Figure 22. Plastic Leaded Chip Carrier Package Specifications
28-Pin PLCC
* Part Number LXT351PE * Extended Temperature Range (-40 C to 85 C)
C L
C
B
D1 D D A2 A1 F
Inches Dim Min A A1 A2 B C D D1 F 0.165 0.090 0.062
1
A
Millimeters Max 0.180 0.120 0.083 Min 4.191 2.286 1.575
1
Max 4.572 3.048 2.108
.050 BSC (nominal) 0.026 0.485 0.450 0.013 0.032 0.495 0.456 0.021
1.27 BSC (nominal) 0.660 12.319 11.430 0.330 0.813 12.573 11.582 0.533
1. BSC--Basic Spacing between Centers.
Datasheet
45
LXT351 -- T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation
Figure 23. Plastic Quad Flat Package Specifications
44-Pin PQFP
* Part Number LXT351QE * Extended Temperature Range (-40 C to 85 C)
D D1 D3 e
E1 E3
E 3 L1 A A2 A1 L B 3
Inches Dim Min A A1 A2 B D D1 D3 E E1 E3 e L L1 q3 q - 0.010 0.077 0.012 0.510 0.390
1
Millimeters Max 0.096 - 0.083 0.018 0.530 0.398 Min - 0.25 1.95 0.30 12.95 9.90
1
Max 2.45 - 2.10 0.45 13.45 10.10
0.315 BSC (nominal) 0.510 0.390
1 1
8.00 BSC (nominal) 12.95 9.90
1
0.530 0.398
13.45 10.10
0.315 BSC (nominal) 0.031 BSC (nominal) 0.029 0.041
8.00 BSC (nominal) 0.80 BSC1 (nominal) 0.73 1.03
0.063 BSC1 (nominal) 5 0 16 7
1.60 BSC1 (nominal) 5 0 16 7
1. BSC--Basic Spacing between Centers.
46
Datasheet

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